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MAX5309EUE Rev. A
RELIABILITY REPORT FOR MAX5309EUE PLASTIC ENCAPSULATED DEVICES
March 30, 2004
MAXIM INTEGRATED PRODUCTS
120 SAN GABRIEL DR. SUNNYVALE, CA 94086
Written by
Reviewed by
Jim Pedicord Quality Assurance Reliability Lab Manager
Bryan J. Preeshl Quality Assurance Executive Director
Conclusion The MAX5309 successfully meets the quality and reliability standards required of all Maxim products. In addition, Maxim's continuous reliability monitoring program ensures that all outgoing product will continue to meet Maxim's quality and reliability standards. Table of Contents I. ........Device Description II. ........Manufacturing Information III. .......Packaging Information V. ........Quality Assurance Information VI. .......Reliability Evaluation IV. .......Die Information .....Attachments
I. Device Description A. General The MAX5309 is a10-bit, eight channel, low-power, voltage-output, digital-to-analog converters (DAC) in a spacesaving 16-pin TSSOP package. The wide +2.7V to +5.5V supply voltage range and less than 215A (max) supply current per DAC is excellent for low-power and low-voltage applications. The low 2nV-s glitch energy of the MAX5309 makes it ideal for digital control of fast-response, closed-loop systems. The MAX5309 has a hardware reset input (CLR-bar) which clears all registers and DACs to zero. The MAX5309 has a software shutdown feature that reduces the supply current to 1A. The MAX5308 features a load DAC (LDAC-bar) function that updates the output of all eight DACs simultaneously. The 3-wire SPITM, QSPITM, MICROWIRETM and DSP-compatible serial interface allows the input and DAC registers to be updated independently or simultaneously with a single software command. This device uses a double-buffered design to minimize the digital-noise feedthrough from the digital inputs to the outputs. The MAX5309 operating temperature range is from -40C to +85C
B. Absolute Maximum Ratings Item VDD to GND All Other Pins to GND Maximum Current Into Any Pin Operating Temperature Range Junction Temperature Storage Temperature Range Lead Temperature (soldering, 10s) Continuous Power Dissipation (TA = +70C) 16-Pin TSSOP Derates above +70C 16-Pin TSSOP
Rating -0.3V to +6V -0.3V to (VDD + 0.3V) 50mA -40C to +85C +150C -65C to +150C +300C 775mW 9.4mW/C
II. Manufacturing Information A. Description/Function: B. Process: C. Number of Device Transistors: D. Fabrication Location: E. Assembly Location: F. Date of Initial Production: Low-Power, Low-Glitch, Octal 10-Bit Voltage-Output DACs with Serial Interface S6 (Standard 0.6 micron silicon gate CMOS) 19,000 California, USA Malaysia or Thailand July, 2001
III. Packaging Information A. Package Type: B. Lead Frame: C. Lead Finish: D. Die Attach: E. Bondwire: F. Mold Material: G. Assembly Diagram: H. Flammability Rating: I. Classification of Moisture Sensitivity per JEDEC standard J-STD-020-A: 16-Pin TSSOP Copper Solder Plate Silver-Filled Epoxy Gold (1 mil dia.) Epoxy with silica filler #05-3901-0002 Class UL94-V0
Level 1
IV. Die Information A. Dimensions: B. Passivation: C. Interconnect: D. Backside Metallization: E. Minimum Metal Width: F. Minimum Metal Spacing: G. Bondpad Dimensions: H. Isolation Dielectric: I. Die Separation Method: 102 x 141 mils Si3N4/SiO2 (Silicon nitride/ Silicon dioxide) Aluminum/Si (Si = 1%) None 0.6 microns (as drawn) 0.6 microns (as drawn) 5 mil. Sq. SiO2 Wafer Saw
V. Quality Assurance Information A. Quality Assurance Contacts: Jim Pedicord (Manager, Rel Operations) Bryan Preeshl (Executive Director) Kenneth Huening (Vice President) 0.1% for all electrical parameters guaranteed by the Datasheet. 0.1% For all Visual Defects.
B. Outgoing Inspection Level:
C. Observed Outgoing Defect Rate: < 50 ppm D. Sampling Plan: Mil-Std-105D VI. Reliability Evaluation A. Accelerated Life Test The results of the 135C biased (static) life test are shown in Table 1. Using these results, the Failure Rate () is calculated as follows: = 1 = MTTF 1.83 192 x 4389 x 79 x 2 (Chi square value for MTTF upper limit)
Temperature Acceleration factor assuming an activation energy of 0.8eV = 13.75 x 10-9 = 13.75 F.I.T. (60% confidence level @ 25C)
This low failure rate represents data collected from Maxim's reliability monitor program. In addition to routine production Burn-In, Maxim pulls a sample from every fabrication process three times per week and subjects it to an extended Burn-In prior to shipment to ensure its reliability. The reliability control level for each lot to be shipped as standard product is 59 F.I.T. at a 60% confidence level, which equates to 3 failures in an 80 piece sample. Maxim performs failure analysis on any lot that exceeds this reliability control level. Attached Burn-In Schematic (Spec. # 06-5814) shows the static Burn-In circuit. Maxim also performs quarterly 1000 hour life test monitors. This data is published in the Product Reliability Report (RR-1M). B. Moisture Resistance Tests Maxim pulls pressure pot samples from every assembly process three times per week. Each lot sample must meet an LTPD = 20 or less before shipment as standard product. Additionally, the industry standard 85C/85%RH testing is done per generic device/package family once a quarter. C. E.S.D. and Latch-Up Testing The DB06 die type has been found to have all pins able to withstand a transient pulse of 1500V per MilStd-883 Method 3015 (reference attached ESD Test Circuit). Latch-Up testing has shown that this device withstands a current of 250mA.
Table 1 Reliability Evaluation Test Results MAX5309EUE TEST ITEM TEST CONDITION FAILURE IDENTIFICATION SAMPLE SIZE NUMBER OF FAILURES
PACKAGE
Static Life Test (Note 1) Ta = 135C Biased Time = 192 hrs. Moisture Testing (Note 2) Pressure Pot Ta = 121C P = 15 psi. RH= 100% Time = 168hrs. Ta = 85C RH = 85% Biased Time = 1000hrs.
DC Parameters & functionality
79
0
DC Parameters & functionality
TSSOP
77
0
85/85
DC Parameters & functionality
77
0
Mechanical Stress (Note 2) Temperature Cycle -65C/150C 1000 Cycles Method 1010 DC Parameters & functionality 77 0
Note 1: Life Test Data may represent plastic DIP qualification lots. Note 2: Generic Package/Process data
Attachment #1 TABLE II. Pin combination to be tested. 1/ 2/
Terminal A (Each pin individually connected to terminal A with the other floating) 1. 2. All pins except VPS1 3/ All input and output pins
Terminal B (The common combination of all like-named pins connected to terminal B) All VPS1 pins All other input-output pins
1/ Table II is restated in narrative form in 3.4 below. 2/ No connects are not to be tested. 3/ Repeat pin combination I for each named Power supply and for ground (e.g., where VPS1 is VDD, VCC, VSS, VBB, GND, +VS, -VS, VREF, etc). 3.4 a. b. Pin combinations to be tested. Each pin individually connected to terminal A with respect to the device ground pin(s) connected to terminal B. All pins except the one being tested and the ground pin(s) shall be open. Each pin individually connected to terminal A with respect to each different set of a combination of all named power supply pins (e.g., V , or V SS1 SS2 or V SS3 or V CC1 , or V CC2 ) connected to terminal B. All pins except the one being tested and the power supply pin or set of pins shall be open. Each input and each output individually connected to terminal A with respect to a combination of all the other input and output pins connected to terminal B. All pins except the input or output pin being tested and the combination of all the other input and output pins shall be open.
c.
TERMINAL C
R1 S1 R2
TERMINAL A REGULATED HIGH VOLTAGE SUPPLY
S2 C1
DUT SOCKET
SHORT CURRENT PROBE (NOTE 6)
TERMINAL B
R = 1.5k C = 100pf
TERMINAL D Mil Std 883D Method 3015.7 Notice 8
ONCE PER SOCKET
ONCE PER BOARD
20 OHMS 4.7 K
+5V CLK1 1KHz
10 uF
0.1 uF 1 2 3 4
CD40161BM
16 15 14 13 12 11 10 9
2 OHMS
5
+5V
6 7
47 K 1 2 3 4 2K 5 2K 6 2K 7 2K 8 9 10 11 12
4.7K
16 - TSSOP
16 47 K 15 14 13 2K 2K 2K
0.1 uF
8
1 2K 2 3 4 5 6 7
MC14013BD
14 13 12 11 10 9 8
DEVICES: MAX5306/5307/5308/5309 MAX. EXPECTED CURRENT = 25mA
DOCUMENT I.D. 06-5814 REVISION B
DRAWN BY: HAK TAN NOTE 1: CD40161BM AND MC14013BD ARE TO BE BUILT 1 PER BOARD NOTE 2: ALTHOUGH SHOWN AT 1kHz. CLK1 CAN BE DC TO 1MHz NOTE 3: AT LEAST 48 CLOCK PULSES MUST BE SENT TO EN SURE DUT IS CORRECTLY SET UP ( DUE TO UNKNOWN FLIP-FLOP/ COUNTER STATES ON POWER - UP ) NOTE 4: LOGIC ENSURES THAT EXACTLY 16 FALLING CLOCK EDGES ARE APPLIED TO DUT WHILE ST CS_BAR IS SLOW. LOADING 16 ' 1 ' S INTO THE SERIAL SHIFT REGISTER
MAXIM
TITLE: BI
Circuit (MAX5306/5307/5308/5309)
PAGE
2
OF 3

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